----------------------------------------------------------------------------------
-- Company:        EECS 452
-- Engineer:       Kurt Metzger
-- 
-- Create Date:    10:55:37 04/05/2008 
-- Design Name: 
-- Module Name:    Camer0Top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Camer0Top is
    Port ( blu : out  STD_LOGIC;
           grn : out  STD_LOGIC;
           red : out  STD_LOGIC;
           hs : out  STD_LOGIC;
           vs : out  STD_LOGIC;
			  red2 : out STD_LOGIC_VECTOR (2 downto 0);
			  grn2 : out STD_LOGIC_VECTOR (2 downto 0);
			  blu2 : out STD_LOGIC_VECTOR (2 downto 1);
			  hs2 : out STD_LOGIC;
			  vs2 : out STD_LOGIC;
			  camera : in STD_LOGIC_VECTOR (7 downto 0);
			  cam_HREF, cam_PCLK, cam_VSYN : in STD_LOGIC;
			  cam_PWDN, cam_RST : out STD_LOGIC;
           cam_SDAS : inout STD_LOGIC;
           cam_scl : out STD_LOGIC;
           ram_addr : out  STD_LOGIC_VECTOR (17 downto 0);
           ram_b_data : inout  STD_LOGIC_VECTOR (15 downto 0);
           ram_we : out  STD_LOGIC;
           ram_oe : out  STD_LOGIC;
           ram_a_ce : out  STD_LOGIC;
           ram_b_ce : out  STD_LOGIC;
           ram_b_lb : out  STD_LOGIC;
           ram_b_ub : out  STD_LOGIC;
			  led : out  STD_LOGIC_VECTOR (7 downto 0);
           btn : in STD_LOGIC_VECTOR (3 downto 0);
           swt : in STD_LOGIC_VECTOR (7 downto 0);
           an : inout STD_LOGIC_VECTOR (3 downto 0);
           ssg : out STD_LOGIC_VECTOR (7 downto 0);
			  
			  fsx0 : out  STD_LOGIC;
           clkx0 : out  STD_LOGIC;
           dx0 : in  STD_LOGIC;
           fsr0 : out  STD_LOGIC;
           clkr0 : out  STD_LOGIC;
           dr0 : out  STD_LOGIC;
			  pmod : inout STD_LOGIC_VECTOR (3 downto 0);
           --pmod_a : out  STD_LOGIC_VECTOR (3 downto 0));
           --swt : in  STD_LOGIC_VECTOR (7 downto 0);
           --ssg : out  STD_LOGIC_VECTOR (7 downto 0);
           --an : inout  STD_LOGIC_VECTOR (3 downto 0);
           --led : out  STD_LOGIC_VECTOR (7 downto 0);
           --mclk : in  STD_LOGIC);
			  
           LeftPWMout : out  STD_LOGIC; --PWM for left wheel
           RightPWMout : out  STD_LOGIC; --PWM for Right wheel
			  Leftout : out STD_LOGIC_VECTOR (1 downto 0);
			  Rightout : out STD_LOGIC_VECTOR (1 downto 0);

           mclk : in  STD_LOGIC);
end Camer0Top;

architecture Behavioral of Camer0Top is
 
	signal Active : std_logic;
	signal Haddr, Vaddr : std_logic_vector(9 downto 0);
	signal clk : std_logic;
   signal ram_address : std_logic_vector(17 downto 0);
	signal display_data : std_logic_vector(31 downto 0);
	signal display_address : std_logic_vector(17 downto 0);
	signal write_address : std_logic_vector(17 downto 0);
	signal vsyn, hsyn : std_logic;
	signal red_out, grn_out : std_logic_vector (2 downto 0);
	signal blu_out : std_logic_vector (2 downto 1);
	signal write_request, write_ack : std_logic;
	signal write_data : std_logic_vector (15 downto 0);
   signal command : std_logic_vector (15 downto 0);
   signal read_req, read_ack : std_logic;
	signal req_get, ack_get : std_logic;
	signal get_address : std_logic_vector(17 downto 0);
	signal get_data : std_logic_vector(15 downto 0);
	signal rdy_in : std_logic;
	signal data_rx : std_logic_vector(15 downto 0);
	signal strobe : std_logic;
	signal pmod_McB : std_logic_vector(3 downto 0);
	signal timer : std_logic_vector(6 downto 0) := (others=>'0');
	signal ack_out : std_logic;
	signal data_send : std_logic_vector (15 downto 0);
	
	-- signals added for the TSM module by us
	signal write_data_tomcbsp : std_logic_vector (15 downto 0);
	signal rcv_data_frommbscp : std_logic_vector (15 downto 0);
	signal rdy_mcbsp, ack_mcbsp : std_logic;
	
	signal state_num : std_logic_vector(5 downto 0);
	signal mcbspCount : std_logic_vector(15 downto 0);
	
	signal LeftPWMin : STD_LOGIC_VECTOR (6 downto 0);
   signal RightPWMin : STD_LOGIC_VECTOR (6 downto 0);
	signal Leftin : STD_LOGIC; --If 1 go forward else backward
	signal Rightin : STD_LOGIC; --IF 1 go forward else backward

	
	
	-- RAM information we jacked from outside ports
	--signal ram_addr : STD_LOGIC_VECTOR (17 downto 0);
   --signal ram_b_data : STD_LOGIC_VECTOR (15 downto 0);
	
	
begin

	clk <= mclk;
	led (5 downto 0) <= state_num;
	led(7) <= swt(1);
	led(6) <= ack_out;
		
	
--	blu <= Haddr(6) and Active;
--	grn <= Haddr(7) and Active;
--	red <= Active;

	red <= red_out(1) and Active;
	grn <= grn_out(2) and Active;
	blu <= blu_out(2) and Active;
	vs <= vsyn;
	hs <= hsyn;
	
	-- second vga interface on camera board
	
	vs2 <= vsyn;
	hs2 <= hsyn;
	red2 <= red_out;
	grn2 <= grn_out;
	blu2 <= blu_out;
		
		-- connect to 40 pin cable McBSP lines
   
   fsx0 <= pmod_McB(0);     -- McBSP transmitter frame sync  
   fsr0 <= pmod_McB(0);     -- McBSP receiver frame sync
   clkx0 <= pmod_McB(3);    -- McBSP transmitter shift clock
   clkr0 <= pmod_McB(3);    -- McBSP receiver shift clock
   pmod_McB(1) <= dx0;      -- McBSP transmitter output to FPGA
   dr0 <= pmod_McB(2);      -- McBSP receiver input from FPGA
   
   --pmod_c <= pmod_McB;  -- for BASYS use

	
	Syn : entity work.VGAtiming 
	port map (
		VSync => vsyn,
		HSync => hsyn,
		Vaddr => Vaddr,
		Haddr => Haddr,
		Active => Active,
		clk => clk);
		     
   ram_a_ce <= '1'; -- don't use
	ram_b_ce <= '0'; -- use
   ram_b_lb <= '0';
   ram_b_ub <= '0';
   ram_addr <= ram_address; 	
	 
	cam_RST <= '0';
	cam_PWDN <= '0';
	
----------------------------------------------------



	OV : entity work.OV6220
	port map (
		CamLines => camera,                -- camera lines into module
		CamHREF => cam_HREF,               -- active area in a scan line
		camPCLK => cam_PCLK,               -- camera pixel clock
		camVSYN => cam_VSYN,               -- camera vertical sync
		CamPixelAddr => write_address,     -- output address
		CamPixelPair => write_data,        -- two pixels in 16 bits out from module
		CamPixWrite => write_request,      -- request writing the pair
      CamPixAckIn => write_ack,
		clk => clk);				
			   
   Cam_com : entity work.CamCom
   port map (
      CamSCL => cam_scl,
      CamSDAS => cam_sdas,
      command => command,
    --  led => led,
      btn => btn,
      swt => swt,
      clk => clk);
      
   sseg : entity ssd02
   port map (
      ssd0 => "0000", --mcbspCount(3 downto 0),
      ssd1 => "0010", --mcbspCount(7 downto 4),
      ssd2 => "0001", --mcbspCount(11 downto 8),
      ssd3 => "0000", --mcbspCount(15 downto 12),
      dp => "0000",
      ssd => ssg,
      sel => "1111",
      an => an,
      clk => clk);


----------------------------------------------------		
		
	DisplayMan : entity work.DisplayManager
	port map (
		Haddr => Haddr,
		Vaddr => Vaddr,
		red => red_out,
		grn => grn_out,
		blu => blu_out,
      active => Active,
      req_out => read_req,
      ack_in => read_ack,
		display_address => display_address,
		data_in => display_data,
		clk => clk);


	MemMan : entity work.MemoryManager
	port map (
		write_address => write_address, -- two pixels per word
		write_data => write_data,
		req_write => write_request,
		ack_write => write_ack,
		display_address => display_address,
		display_data => display_data,
      ram_address => ram_address,
		ram_data => ram_b_data,
      req_read => read_req,
      ack_read => read_ack,
		req_get => req_get,
		ack_get => ack_get,
		get_address => get_address,
		get_data => get_data,
      we_n => ram_we,
		oe_n => ram_oe,
		clk => clk);


--	McBSP : entity work.metastabletop
--	port map (
--		fsx0 => fsx0,
--      clkx0 => clkx0,
--      dx0 => dx0,
--      fsr0 => fsr0,
--      clkr0 => clkr0,
--      dr0 => dr0,
--		ram_data => ram_b_data,
--		--pmod_a => pmod_a,
--		--swt => swt,
--		--ssg => ssg,
--		--an => an,
--		--led => led,
--		mclk => clk,
--		data_rx => data_rx);
--         
   McB : entity work.McBSPXmtr2
   port map ( --data_send => ram_b_data, -- data to McBSP
					data_send => data_send,
               data_rcvd => data_rx, 	-- data from McBSP
               rdy_in => rdy_in,     	-- set high to send value to McBSP
					ack_out => ack_out,
               pmod => pmod_McB,       -- connect to Pmod connecting FPGA/DSK
               clk => clk,
               reset => swt(1));

	TSM : entity work.TransferStateMachine
	port map ( req_get_memman => req_get,
				  ack_get_memman => ack_get,
				  get_address_memman => get_address,
				  get_data_memman => get_data,
				  write_data_tomcbsp => data_send,
				  rcv_data_frommbscp => data_rx,
				  rdy_mcbsp => rdy_in,
				  ack_mcbsp => ack_out,
				  
				  Anna => mcbspCount,
				  SN => state_num,
				  clk => mclk);
				  
				  
	PWM : entity work.PWMtop 
	port map(	LeftPWMin  => LeftPWMin,
					RightPWMin => RightPWMin,
					Leftin => Leftin,
					Rightin => Rightin,
					LeftPWMout => LeftPWMout,
					RightPWMout => RightPWMout,
					Leftout => Leftout,
					Rightout => Rightout,
					mclk => mclk);
				  

end Behavioral;

